As physical performances of traditional CMOS devices gradually approach the quantum limit, there is an urgent demand for high-performance electronic systems. System-on-chip (SOC) is becoming a solution of the semiconductor industry. As for a SOC, various functions are integrated on one chip. Although forming a circuit on a silicon substrate is currently a mainstream for forming an ultra-large-scale device, it is better to form a device and/or circuit on a non-silicon substrate to obtain the required circuit or photoelectric functions. Therefore, a mixed system including a silicon-based device and a non-silicon-based device, rather than an individual one of them, may be a practical way to obtain a certain SOC function.
Forming a heterogeneous material on a silicon substrate with heteroepitaxial growth is one of the ways to form a heterogeneous device. Nowadays, a heteroepitaxial film formed by heteroepitaxial growth has a drawback of high density, which is mainly due to the lattice constant mismatch between a non-silicon-based film and a silicon substrate.
Another method for forming a heterogeneous device is wafer bonding. However, during the wafer bonding processes, because different materials have different thermal expansion coefficients, the thermal stresses generated in the heating process may cause dislocation, peeling or cracking. Therefore, the wafer bonding needs to be performed at a low temperature, especially for those materials having a lower decomposition temperature or temperature-sensitive devices, such as InP heterojunction bipolar transistor or silicon devices with ultra-shallow source and drain. Than is, the low temperature wafer bonding process is very important for different materials.
It is difficult to manufacture a chip having different functions and different materials and the processes are difficult to be optimized, resulting in a low yield for many SOCs, especially for those in large-scale integration. One solution is to make the process compatible with IC process by wafer bonding. However, wafer bonding is generally performed at a high temperature, which may lead to thermal stresses, bubbles and instable adhesions, resulting in a low yield and poor reliability.
Direct wafer bonding is a kind of technology for bonding wafers at a low temperature without any adhesive. The direct wafer bonding is performed in vacuum environment. The bonding process is performed at a low temperature, generally at room temperature, so no thermal stresses and heterogeneity will be introduced and it enables to produce more reliable circuits. Further, if a bonded wafer is processed by a thinning process and is thinned to have a thickness less than the respective critical values of combined materials, layer dislocation, slip or cracking may be avoided in subsequent heat treatments.
Furthermore, direct wafer bonding and layer transfer is compatible with the very large scale integration (VLSI) circuit, namely, it is feasible and manufacturable, and it is very practical to use this technique to form a stacked three-dimensional SOC. The three-dimensional SOC is to form a system by integrating existing integrated circuits on a chip.
At low temperatures, it is practical to form a three-dimensional SOC by direct bonding between wafers or chips, which may electrically connect the wafers or chips. Besides, non-metal regions of the wafers or chips may be directly bonded, therefore, post-treatment processes after bonding, such as substrate thinning, etching, metal interconnecting, may be avoided, and namely, the process are optimized. Furthermore, parasitics caused by small metal bonding pads are minimized, which may reduce power consumption and increase bandwidth.
Currently, in the VLSI technology, copper interconnect has become a mainstream. However, copper has a high diffusion rate in silicon and silica, therefore, copper is likely to diffuse into an active area including silicon and damage the device, thereby causing junction or silicon oxide leakage currents. A barrier layer may be employed to overcome copper diffusion and increase the adhesion between copper and silicon oxide, however, during the bonding process, a chemical bond may not be formed in the barrier layer on silicon oxide, resulting in a weak bonding strength. On the other hand, the adhesion between copper and silicon oxide is poor, so that depositing copper on a silicon wafer may be difficult and copper may not stick to the silicon wafer, resulting in poor mechanical and electrical connection between wafers. Furthermore, even in the air at a low temperatures (such as less than 200° C.), copper is also likely to be oxidized, and a protective layer will not be formed to prevent further oxidation. Besides, while bonding a metal with another metal, a gap may be formed around the bonding area, and the gap may be increased when the height of a metal pad is increased, which may reduce the bonding strength and increase post treatment after bonding.